1. Technical Field
The technical field relates to an analog-to-digital converter (ADC), and more particularly to a successive approximation register analog-to-digital converter (SAR ADC) and a method of linearity calibration therein.
2. Related Art
In recent years, integrated circuit design has been trending towards increasingly difficult demands on lowering power consumption and cost along with enhancing performance. In the design of front-end analog circuits, an efficient analog-to-digital converter (ADC) can drastically enhance the overall system performance. The ADC is responsible for converting the received analog signals into digital signals, and providing the digital signals for the operation of the back-end digital signal processing unit. Therefore, characteristics of the ADC such as its dynamic range, resolution, accuracy, linearity, sampling speed, power consumption, and its input stage are crucial factors which influence the overall system performance, and these characteristics serve as several parameters for evaluating the performance of the ADC.
For two categories in resolution and sampling speed, the application range of an ADC with 8-14 bits and one to several hundred mega samples per second (MSPS) is quite broad. Applications such as in the front-end of the base frequency or the intermediate frequency of a communication system, a biomedical imaging process such as the front-end of a ultrasonic imaging system, and the front-end of a laser array system are all within the range of applications. The ADC has many types of configurations, and when manufacturing an ADC matching the aforementioned specifications, a diverse array of configurations can be chosen. The mainstream ADC applied commercially is the pipeline analog-to-digital converter, or the pipeline ADC. However, in recent years, articles in prominent international journals have gravitated towards the successive approximation register analog-to-digital converter (SAR ADC) as a popular research direction, because the SAR ADC configuration almost does not require a direct current bias voltage. Since the SAR ADC requires a good amount of digital circuits for control and signal processing, when the manufacturing process enters the deep sub-micron, the chip area and the power consumption needed for a portion of the digital circuits can be effectively reduced. Accordingly, the SAR ADC is suitable for developing the intellectual property from a large scale system-on-chip (SoC). In many disclosures, the SAR ADC has lower consumption and smaller chip area when compared to the pipeline ADC with the same specification requirements. Therefore, the technical development of the SAR ADC framework has become an active field of research.
However, a major functional block exists in the SAR ADC configuration: the digital-to-analog converter (DAC), which directly influences the performance of the SAR ADC. Due to the strong necessity of matching among each of the composed elements in the DAC, such as the capacitor, the DAC takes up a significant portion of the overall chip area and the power consumption of the SAR ADC. Thus, when the DAC requires a larger area, the driving circuit of the DAC also requires a larger driving force, and this further increases the area and power consumption. Since the cost of digital circuits is low, if the matching requirement the DAC places on each of the composed elements can be reduced or eliminated by adopting processing techniques using digital circuits, the overall chip area and power consumption of the ADC can be lowered.
FIG. 1 is a simplified circuit diagram of a SAR ADC. Please refer to FIG. 1. A SAR ADC 10 includes a DAC 12, a comparator 16, and a successive approximation register logic (SAR logic) circuit 18. The DAC 12 includes a plurality of switches S0, S1, S2, S3, Sr, Si, and Sg and four composed capacitors C0, C1, C2, and C3, and all of the first terminals of the composed capacitors are coupled to a same node X. A first terminal of a reference capacitor Cr is also coupled to the afore-described node X. During a sampling mode, the switches S0, S1, S2, S3, and Sr are switched to conduct to the switch Si, and the switch Si is switched to conduct to an input voltage Vin. The switch Sg is conducted so the capacitors C0, C1, C2, C3, and Cr are charged to the input voltage Vin. Thereafter, the switch Sg is broken off and non-conductive, and the switches S0, Si, S2, S3, and Sr are switched to conduct to the ground voltage level, so the voltage at the node X becomes −Vin. During a conversion mode, the switch Si is switched to conduct to the reference voltage Vref, the switch Sg is broken off, and the switches S0, S1, S2, and S3 are switched according to a 4-bit control signal. After the successive approximation, when the voltage at the afore-described node X approaches 0, that is, when the equivalent open circuit outputs of the two modes are approximately equal, the final ADC digital output value can be calculated and obtained according to the 4-bit control signal.
The capacitors of the DAC depicted in FIG. 1 have a capacitance of radix 2, that is:C=2n*C, in which n is a positive integer greater than or equal to 0 and less than 4. Therefore, after the successive approximation, the SAR logic circuit 18 transmits a 4-bit control signal to the DAC 12, that is the last ADC digital output value ADCOUT, in which all of the bit values D0, D1, D2, and D3 of the control signal equals 0 or 1. However, the linearity of the ADC is directly affected by the difference between the actual value and the ideal value of the capacitor.